Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation.
Your Role
Key responsibilities in your new role
Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation.
MUST have:
Good understanding of modelling technique for Analog Blocks using Verilog and System Verilog.
Good exposure on digital verifications,
Ability to interact and work with team member in multiple geography.
Good exposure to dotlib generation.
Added advantage:
Exposure to the MSV simulation flow.
Basic understanding of analog circuits.
Your Profile
Qualifications and skills to help you succeed
BS/MS in Electrical Engineering
Bachelor's - 6 to 11 years’ experience, Master’s - 4 to 10 years’ experience.
Very good knowledge of Verilog/System Verilog and UVM.
Should be a good mentor and guide for junior engineers in the team.
Candidate should have worked on AMS/Digital Block Modelling based RNM modelling.
Exposure to deployment of automation and formal verification methodologies is a plus.
Contact:
[email protected]
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📌 Staff Engineer Design (Bengaluru)
🏢 infineon
📍 Bengaluru