ASIC DFT Engineer | 8+ years | DFT/ATPG/MBIST/SCAN/JTAG (Bengaluru)

ASIC DFT Engineer | 8+ years | DFT/ATPG/MBIST/SCAN/JTAG (Bengaluru)

16 Aug
|
Cisco
|
Bengaluru

16 Aug

Cisco

Bengaluru

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Your Impact
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.




- Responsible for development of creative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

You are an ASIC Design for Test Hardware Engineer with 8-10 years of related work experience with a broad mix of technologies.

Minimum Qualifications:
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 8-10 years of experience.
- Knowledge of the latest innovative trends in DFT, test and silicon engineering.
- Experience with Jtag protocols, Scan insertion and ATPG.
- Experience with ATPG and EDA

📌 ASIC DFT Engineer | 8+ years | DFT/ATPG/MBIST/SCAN/JTAG (Bengaluru)
🏢 Cisco
📍 Bengaluru

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