Our vision is to transform how the world uses information to enrich life for
all.
Micron Technology is a world leader in innovating memory and storage solutions
that accelerate the transformation of information into intelligence, inspiring
the world to learn, communicate and advance faster than ever.
For more than 45 years, Micron Technology, Inc. has redefined innovation with
the world’s most advanced memory and semiconductor technologies. We’re an
international team of visionaries and scientists, developing groundbreaking
technologies that are transforming how the world uses information to enrich
life.
We are looking for Layout Design engineer at our Micron Technology’s
DPG-IPDEV Team in Bangalore, India. DPG-IPDEV team is responsible for
developing world-class analog and mixed signal IPs used in every cutting edge
DRAM chip produced in Micron. As a Layout Design engineer, you will be working
for intensive applications such as artificial intelligence and high-performance
computing solution, High Bandwidth Memory. As a Layout Design Engineer you will
be collaborating with peer teams crossing Micron global footprint, in a multiple
projects-based environment.
Role and Responsibilities
• Responsible for Design and development of critical analog,
mixed-signal, custom digital block, and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and
support documentation.
• Responsible for timely delivery of block-level layouts with acceptable
quality.
• Demonstrate leadership qualities in planning, area/time estimation,
scheduling, and execution to meet project schedule/milestones in multiple
project workplace.
• Contribute to effective project-management.
• Effectively communicating with Global engineering teams to assure the
success of layout project.
Qualification/Requirements
• 5 to 8 years' experience in analog/custom layout build in advanced CMOS
process, in various technology nodes (Planar, FinFET )