Industry Type : Education/E-Learning/Semiconductor
Job Type : Training
Job Description
- Extensive hands on and teaching experience on Digital/SV/UVM/Verilog/VHDL /DFT tools
- Experience on Mentor Graphics EDA flow/Cadence Tool/Synopsys Tool is an added advantage
- Responsible for development and support of Projects.
- Responsible for Debugging the source codes in Verilog, SV, and UVM.
- Responsible for Training Delivery and Support
Mandatory Requirements
- Sound Knowledge on Digital/Verilog /VHDL/SV/UVM/DFT/Physical Design
- 3 to 8 years Industry/Teaching/Training experience
- Valuable communication skills