Project Role : Design-For-Test (DFT) Engineer

Project Role Description : Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.

Must have skills : Design for Testability (DFT)

Good to have skills : NA

Minimum 3 year(s) of experience is required

Educational Qualification : 15 years full time education

Summary

As a Design-For-Test Engineer, your day involves embedding testability features into chip designs to facilitate thorough post-manufacturing testing. You work closely with various teams to integrate methodologies that improve defect detection and test coverage.

Your role ensures that the silicon produced meets high standards of quality by optimizing test efficiency and enabling precise fault isolation. This position requires a proactive approach to problem-solving and continuous collaboration to enhance the overall testing process throughout the design lifecycle.

Roles & Responsibilities:

- Expected to perform independently and become an SME.
- Required active participation/contribution in team discussions.
- Contribute in providing solutions to work related problems.
- Collaborate with cross-functional teams to align design and test strategies for optimal results.
- Continuously evaluate and implement current test methodologies to improve product quality.
- Document and communicate test design processes and outcomes effectively to stakeholders.

Professional & Technical Skills:
- Must To Have Skills: Proficiency in Design for Testability (DFT).
- Strong knowledge of scan chain insertion and optimization techniques.
- Experience with Built-In Self-Test (BIST) architectures and boundary scan implementation.
- Ability to analyze and troubleshoot test coverage and fault isolation issues.




- Familiarity with silicon validation and post-silicon debug processes.

Additional Information

- The candidate should have minimum 3 years of experience in Design for Testability (DFT).
- This position is based at our BDC6F - SEZ office.
- A 15 years full time education is required.

15 years full time educationAbout Accenture

Accenture is a leading global professional services company that helps the world’s leading businesses, governments and other organizations build their digital core, optimize their operations, accelerate revenue growth and enhance citizen services—creating tangible value at speed and scale. We are a talent- and innovation-led company with approximately 791,000 people serving clients in more than 120 countries. Technology is at the core of change today, and we are one of the world’s leaders in helping drive that change, with strong ecosystem relationships.

We combine our strength in technology and leadership in cloud, data and AI with unmatched industry experience, functional expertise and global delivery capability. Our broad range of services, solutions and assets across Strategy & Consulting, Technology, Operations, Industry X and Song, together with our culture of shared success and commitment to creating 360° value, enable us to help our clients reinvent and build trusted, lasting relationships. We measure our success by the 360° value we create for our clients, each other, our shareholders, partners and communities.Visit us at www.accenture.com

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📌 Design-For-Test (DFT) Engineer (Bengaluru)
🏢 Accenture
📍 Bengaluru