Building next-generation AI compute platforms and silicon that deliver breakthrough performance, efficiency, and scalability. Our cross-functional hardware, software, and silicon teams collaborate closely to push the boundaries of edge and cloud AI acceleration. We are expanding our SoC Architecture & Design team in Hyderabad to support our rapidly growing AI silicon roadmap.
Role Overview
We are seeking a Mid-Level SoC Design Engineer with solid expertise in ARM architecture and hands-on experience working with Arm Corestone reference systems. The role involves supporting subsystem design, integration, and optimization activities across AI’s next-generation SoCs.
In addition, we are looking for engineers with a solid background in ASIC SoC and RTL design, with an emphasis on front-end ASIC design techniques and methodologies. You will collaborate with architecture, verification,
and physical design teams to bring complex ARM-based subsystems to production-quality readiness.
Key Responsibilities
• Design and integrate ARM-based subsystems derived from Arm Corestone reference packages into AI SoCs.
• Implement and modify RTL for CPU subsystems, AMBA interconnects, memory controllers, and peripheral IP.
• Collaborate with architecture teams on feature definition, microarchitecture updates, and performance targets.
• Work closely with verification teams to debug functional issues and ensure high-quality coverage closure.
• Support synthesis, timing analysis, and physical design teams during SoC execution.
• Drive documentation, design reviews, and bring-up support for early silicon and emulation platforms.
• Contribute to methodology improvements for subsystem integration and design scalability.
Required Qualifications
• Bachelor’s or Master’s degree in Electrical Eng