MaxLinear is seeking a Principal ASIC Design Engineer to join our Digital ASIC Design group. The Digital ASIC team delivers innovative and scalable ASIC solutions addressing complex challenges in the optical and wireless communications domain.
In this senior technical role, you will lead the architecture, micro-architecture, and RTL design of high-performance packet processing, interface, and system control blocks. You will also be responsible for the integration of these logic components along with custom or 3rd party embedded processors in multi-CPU SoC environments, contributing to highly integrated and power-efficient designs.
This position requires expertise in packet processing architectures, understanding of computer networking fundamentals, strong grounding in digital design and CMOS logic, and experience applying industry-standard design and verification methodologies. Proficiency with up-to-date design and verification tools is essential. Experience with low-power design techniques is highly desirable.
The ideal candidate is a curious,
highly motivated engineer with a relentless drive to learn, innovate, and solve complex problems. You bring a “never give up” attitude and thrive when tackling technically demanding challenges. You value collaboration across disciplines and leverage the differences in skill sets with cross-domain teams to contribute to collective problem-solving. You aspire to make a lasting technical impact while continuously raising the bar for design quality and engineering excellence.
Qualifications
- BE/M.Tech in Electronics Engineering
- 15+ years of experience in Digital ASIC implementation at subsystem level or chip level including RTL design skills using Verilog, System Verilog or VHDL
- Strong analytical and problem-solving skills
- Proved expertise in translating engineering requirements to working ASIC solutions meeting PPA
- Strong fundamentals and proven expertise in digital logic design, CMOS technology and A
📌 Principal ASIC Design Engineer (Bengaluru)
🏢 MaxLinear
📍 Bengaluru
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