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Responsibilities
- DFT architecture definition
- Understand SoC architecture and test requirements.
- Work very closely with the lead Product/Test engineering throughout the DFT definition phase to determine productive ways to optimize test cost and achieve high test coverage.
- Drive and optimize DFT architecture for high performance and efficiency:
- SCAN – scan partition, compression, at-speed, IR and low power
- MBIST for memories
- JTAG boundary scan insertion




- Handle responsibilities pertaining to both block and top-level activities in Hierarchical Scan.
- Implementation
- Develop / Upgrade SCAN & MBIST Insertion flows
- Develop appropriate timing constraints for SCAN/MBIST modes and debug timing violations
- ATPG flow implementation catering to various fault models, test pattern generation
- SCAN , MBIST & BSCAN Pattern Simulation
- Solutions to test analog macros
- Post-Silicon bring-up/support
- Work with Evaluation/Test Engineering team to bring-up patterns on ATE
- Work on failure analysis as required
- Work with the Operation team on test cost and yield improvement
- Improve DFT methodology to be in sync with latest best practices and technology in the industry
- Work closely with physical design team throughout the development cycle.
- Should be able to guide newly inducted team members on their bring-up on flow, methodology and execution methods in all aspects of DFT.

Requ

📌 Senior DFT Engineer (Bengaluru)
🏢 Analog Devices
📍 Bengaluru