Senior ASIC Design Verification Engineer
This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
What You’ll Do:
- Drive advanced verification using UVM methodology to validate complex ASIC features
- Architect and develop block, subsystem, and full-chip verification environments using SystemVerilog and UVM
- Define,
design, and execute verification plans and test suites for ASICs
- Perform verification using simulation tools (VCS / NC-Sim or equivalent)
- Own end-to-end verification of large ASIC blocks, including coverage analysis and tape-out sign-off
- Perform functional coverage, code coverage, and gate-level simulations (GLS)
- Collaborate with RTL designers for debugging and software teams for bring-up and validation
- Enhance verification infrastructure through automation using Perl, Python, or Shell scripting
What You Need to Bring:
- 15+ years of experience in ASIC Verification using SystemVerilog
- Robust expertise in UVM (preferred), OVM, or VMM methodologies
- Experience in constrained-random verification
- Hands-on experience with ASIC debugging and problem-solving
- Proficiency with simulation tools like VCS / NC-Sim
- Strong scripting skills in Perl / Tcl (Python is a plus)
- Exposure t