AMS Design Verification Layout Engineers (Hyderabad)

AMS Design Verification Layout Engineers (Hyderabad)

17 Aug
|
Tuitions Tree
|
Hyderabad

17 Aug

Tuitions Tree

Hyderabad

Location – Noida, Hyderabad:

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AMS Layout Engineers – 4 Positions

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AMS Design / Verification / Layout Engineers – 8 Positions

Experience: 4 to 10 Years
Job Type: Full-time (On-site)
Notice Period: Immediate to 30 Days preferred

Role Categories:

1. AMS Design Engineer

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Experience in Analog and Mixed Signal circuit design

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Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks

2. AMS Verification Engineer

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Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS

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Valuable exposure to mixed-signal testbench development and verification methodology

3. AMS Layout Engineer

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Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks

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Experience with layout tools such as Virtuoso, Calibre, etc.

Desired Skills:

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Solid understanding of analog and mixed-signal concepts

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Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.)

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Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus)

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Strong communication and collaboration skills

📌 AMS Design Verification Layout Engineers (Hyderabad)
🏢 Tuitions Tree
📍 Hyderabad

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