o Working experience in SOC or Subsystems designs for multiple projects o Strong understanding of DFT methodologies and experience in standard DFT tools.
- Familiarity with SoC style DFT architectures including multi-clock domain and low power design practices.
- Knowledge of DFT including Scan, MBIST
- Knowledge of low power design methodology (static/agile clock gating, power gating,
dynamic voltage and frequency scaling)
- Good experience Top-level clock/reset circuit design
- Knowledge on DFT simulations and debugging.
- Hands On experience in ATPG/SCAN/MBIST/JTAG implementation at chip & block level.
- Knowledge on Test mode timing constraint development and analysis is a plus.
- Understanding of test compression and ATE debug is a plus
📌 DFT engineer (Bengaluru)
🏢 Uni Connect
📍 Bengaluru
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.