Key Responsibilities
- DFT Architecture: Define and implement robust, hierarchical DFT architectures (e.g., IEEE 1500, JTAG, LBIST/MBIST, ATPG, and boundary scan).
- Flow Execution: Execute end-to-end DFT flows, including scan compression and insertion, coverage analysis, and DRC rule checks at both block and top levels.
- Simulation & Verification: Conduct timing/non-timing simulations and static verification to ensure DFT logic does not interfere with functional operations.
- Timing Closure & Layout: Collaborate with physical design and synthesis teams to resolve logic constraints, timing closure, and routing issues introduced by DFT structures.
- Pattern Delivery & Debug: Generate manufacturing/ATE patterns, support post-silicon bring-up, and assist with failure analysis and fault diagnosis.
Technical Requirements
- Education & Experience: Bachelor's or Master's degree in Electronic/Computer Engineering with typically 4 to (12+) years of hands-on semiconductor industry experience.
- EDA Tool Proficiency: Deep expertise in industry-standard tool suites such as Siemens Tessent, Synopsys (TestMAX / TetraMAX), or Cadence Modus.
- Scripting Languages: Robust proficiency in automation and scripting languages like TCL, Python, or Perl.
- Core Competencies: Understanding of fault models, ICL/PDL standards, test point insertion, and high-speed IO or analog DFT testing methodologies.