Job DescriptionJob Title:IP Verification Engineer – UVM verification
nExp Level:4+ yrs
nLocation:Bangalore/Hyderabad
nJob Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.
nDevelop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
nBasic Job Deliverable:Setup verification workplace and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera
nSV/UVM Functional verification
nExpertise in Vivado for simulation debugs
nQualification:B.E/M.E/M.Tech
nInterested can Share CV to

📌 IP Verification Engineer (Karnataka)
🏢 ACL Digital
📍 Karnataka