Lead Physical Design Engineer
Experience: 8–12 Years
Location: Bengaluru
Domain: VLSI / Physical Design
Role
Lead full-chip Physical Design and timing closure for advanced SoC designs, driving implementation from synthesis through signoff.
Core Responsibilities
Own full-chip Physical Design from synthesis, floorplanning, placement, CTS, routing to physical signoff.
Drive STA and timing closure across MMMC/PVT corners with strong focus on setup/hold.
Work on SDC constraints, timing exceptions, clock architecture, OCV/AOCV/POCV, SI and CRPR/CPPR.
Analyze and resolve critical timing, congestion, power, DRC/LVS and signal-integrity issues.
Drive full-chip ECOs and timing convergence across implementation stages.
Collaborate closely with RTL, synthesis, STA, DFT, PD and signoff teams.
Debug complex timing paths and optimize design for PPA and signoff quality.




Develop/maintain PD and STA automation using Tcl/Python/Perl.
Provide technical leadership and mentor PD engineers on implementation and timing closure.
Must-Have Skills
8–12 years hands-on experience in ASIC Physical Design.
Strong full-chip implementation and timing closure experience.
Expert-level knowledge of STA, MMMC, SDC and timing constraints.
Hands-on with PrimeTime/PrimeTime-SI and industry-standard PD tools.
Robust understanding of floorplanning, placement, CTS, routing, ECO and physical signoff.
Experience with advanced-node SoCs and complex hierarchical designs.
Strong debugging, scripting and cross-functional problem-solving skills.
Education
B.E./B.Tech/M.E./M.Tech in Electrical, Electronics, VLSI or related discipline.

📌 Lead Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru