Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of contemporary AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Design Verification Engineer – CXL / PCIe / Ethernet
About Astera Labs
Astera Labs is a global leader in purpose-built semiconductor connectivity solutions for AI and cloud infrastructure.
Our intelligent connectivity platform enables hyperscalers and system OEMs to unlock the full potential of accelerated computing by delivering scalable, high-performance solutions based on industry-leading standards such as PCI Express (PCIe), Compute Express Link (CXL), and Ethernet.
Role Overview
We are seeking an experienced Principal Design Verification Engineer to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.
The ideal candidate is passionate about building world-class verification environments, has deep expertise in protocol verification, and enjoys solving complex architectural challenges.
Key Responsibilities
Technical Leadership
Lead the verification strategy for comple