Location: Bay Area, California (Onsite at Client Location)
Work Mode: Full-Time | Work From Office (WFO)
Work Authorization: Valid US Work Visa Required
About the Role
We are looking for an experienced Senior Design Engineer with strong expertise in So C architecture, RTL development, and high-performance interconnects. The ideal candidate will play a key role in designing next-generation semiconductor solutions for cutting-edge compute and connectivity platforms.
Experience
8–12 Years of Industry Experience
Key Responsibilities
RTL Design & Development
Design and develop synthesizable RTL for:
AMBA AXI4 / AXI5 Interconnects AMBA ACE & CHI Coherent Interfaces DMA Engines Protocol Bridges & Converters Buffering Structures Memory Subsystems interfacing with LPDDR4 / LPDDR5 / LPDDR5 X Controllers PCIe Endpoint, Root Complex, and Subsystem Integration Logic Microarchitecture Development
Define and implement microarchitecture for:
Transaction Ordering Qo S & Arbitration Schemes Cache Coherency Mechanisms Flow Control & Protocol Compliance CDC (Clock Domain Crossing)
RDC (Reset Domain Crossing) Cross-Functional Collaboration
Translate system requirements into detailed microarchitecture specifications. Work closely with architects and verification teams. Develop test plans, coverage strategies, assertions, and protocol compliance checks. Support So C integration, performance tuning, and silicon bring-up activities. Performance & Implementation Support
Analyze and optimize latency, throughput, and power efficiency. Support synthesis, timing closure, and physical design teams throughout implementation. Preferred Skills
Strong RTL coding experience in Verilog/System Verilog
Deep understanding of AXI, ACE, CHI, PCIe, and memory subsystem architectures
Experience with high-performance So C design and integration
Knowledge of CDC/RDC methodologies and verification concepts
Familiarity with synthesis and timing closure flows
Why Join?
Chance to work on advanced So C and semi