Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, versatile systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs is a global leader in semiconductor-based connectivity solutions purpose-built for AI and cloud infrastructure.
Our intelligent connectivity platform enables hyperscalers and system OEMs to unlock the full potential of accelerated computing through industry-leading technologies such as Compute Express Link (CXL), PCI Express (PCIe), and Ethernet.
We are looking for a highly motivated Tech Lead Design Verification Engineer to join our Silicon Engineering team and drive the verification of next-generation connectivity IPs and SoCs that power AI infrastructure and cloud-scale systems.
Role Overview
As a Lead Design Verification Engineer, you will lead the verification of complex digital IPs and SoC subsystems, ensuring high-quality, first-pass silicon. You will own verification planning, environment development, test execution, debugging, and sign-off while working closely with Architecture, Design, Firmware, Emulation, and Validation teams.
This role requires strong technical expertise, hands-on verification experience, and the ability to mentor engineers and drive execution across multiple projects.