Lead ASIC RTL Design Engineer

Exp-(6–12 Years)

Location: Bengaluru, India

Role Overview

We are looking for a highly skilled Lead ASIC RTL Design Engineer with robust expertise in microarchitecture definition, RTL development, and ASIC implementation. The ideal candidate will have hands-on experience in designing high-performance, power-efficient digital IPs and So Cs, translating architectural specifications into robust RTL implementations.

Key Responsibilities
Drive microarchitecture development for complex ASIC/So C blocks, balancing performance, power, area, and scalability requirements. Develop high-quality RTL using Verilog/System Verilog for complex digital designs. Define datapath, control logic, pipeline architecture, clocking strategies, and state machines. Collaborate closely with architecture, verification, physical design, DFT, and firmware teams throughout the development cycle. Create detailed design specifications, microarchitecture documents, and implementation plans. Perform RTL linting, CDC/RDC analysis, low-power checks, and design quality signoff.



Support synthesis, timing closure, power optimization, and silicon bring-up activities. Analyze and resolve functional, timing, and implementation issues across the ASIC development flow. Drive design reviews and ensure adherence to coding guidelines and design methodologies. Required Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field. 6–12 years of ASIC/So C RTL Design experience. Strong expertise in digital design fundamentals, computer architecture, and microarchitecture development. Proficiency in Verilog/System Verilog RTL design. Experience with pipelined architectures, cache controllers, memory subsystems, interconnects, and high-performance datapaths. Strong understanding of ASIC design flow including RTL-to-GDSII. Hands-on experience with synthesis, STA concepts, CDC, RDC, lint, and low-power methodologies. Familiarit

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