Senior Physical Design Lead (Bengaluru)

Senior Physical Design Lead (Bengaluru)

18 Aug
|
Mulya Technologies
|
Bengaluru

18 Aug

Mulya Technologies

Bengaluru

Location: Bengaluru, India

Experience: 5-16 years

Industry: Semiconductors | AI | Networking | ASIC Design

Senior Physical Design Lead - SoC Floorplanning & Integration

Location: Bengaluru, India

Experience: 12-20 years

Industry: Semiconductors | AI | Networking | ASIC Design

Role Overview

We are seeking a hands-on Senior Physical Design Lead to own full-chip SoC physical implementation for our next-generation AI-networking silicon. You will define the top-level floorplan and partitioning strategy, personally drive chip-level integration and convergence, and lead a small team of block/partition owners from netlist to tape-out. This is a working-lead role - you set the SoC floorplan vision and stay hands-on in the tool on the hardest full-chip problems.

Key Responsibilities
- SoC Floorplanning Ownership: Define and own the full-chip floorplan - top-level partitioning, block placement, aspect ratios, macro and IP placement, IO/bump planning, and die-size budgeting.
- Partitioning Strategy: Drive hierarchical partitioning, feedthrough planning,



and pin/budget allocation across partitions to enable parallel block development.
- Top-Level Integration: Own chip-level assembly, top-level routing, clock and reset distribution, and full-chip timing/physical convergence.
- Power Delivery Co-Design: Work with the PDN and EM/IR teams to co-design the power grid and floorplan so power-integrity and reliability targets are met from the start.
- Working Leadership: Lead and mentor block/partition PD engineers while staying hands-on;
set QoR targets and review cadence across the SoC.
- Cross-Functional Alignment: Partner with architecture, RTL, STA, DFT, packaging, and foundry teams to align floorplan and integration decisions.
- Convergence & Tape-out: Drive full-chip timing, congestion, IR, and physical-verification closure and own the SoC through sign-off and tape-out.
- Schedule & Risk: Plan SoC PD milestones, surface floorplan and integration risks early, and drive mi

📌 Senior Physical Design Lead (Bengaluru)
🏢 Mulya Technologies
📍 Bengaluru

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