18 Aug
|
Einfochips
|
Hyderabad
18 Aug
Einfochips
Hyderabad
Roles and Responsibilities :
- Design and develop verification environments using SystemVerilog, UVM, and Python for complex digital designs.
- Collaborate with cross-functional teams to identify requirements and create test plans, cases, and scenarios.
- Develop high-quality code in System Verilog and Synopsys VCS to verify hardware functionality at the chip level.
- Analyze results, debug issues, and provide technical documentation on defects found during testing.
Job Requirements :
- 5-15 years of experience in Design & Verification Engineering with expertise in SystemVerilog, UVM, and Python.
- Robust understanding of digital circuit design principles and ability to write efficient code in System Verilog.
- Experience working with Synopsys VCS toolset including synthesis, simulation, emulation/FPGA-based prototyping.
📌 Design and Verification Engineer (Hyderabad)
🏢 Einfochips
📍 Hyderabad