Role Overview
We are looking for a highly skilled
RTL Designer
to develop high-performance, scalable, and power-efficient digital designs for next-generation SoCs and Chiplets targeting
AI, HPC, and Networking applications
. This role requires deep expertise in RTL design, micro-architecture, and integration of high-speed interfaces, along with a strong focus on
quality, performance, and first-time silicon success
.

What
You’ll
Do
- Specify and own the reset sequencing architecture. Own the secure boot and fuse micro architecture and design.
- Coordinate with the subsystem leads on reference clock distribution, clock-domain crossing points at subsystem interfaces.
- Collaborate with the firmware team to define the hardware/software interface: interrupt controller, timer, UART/JTAG debug port, and any DMA or mailbox channels
- Own the clock-gating implementation strategy: coarse-grain vs. fine-grain gating, ICG cell selection, and sign-off methodology for dynamic power reduction.
- Define the chip-level power-domain plan: which blocks share supplies,



where level-shifters and isolation cells are required, and how power states map to the PCIe and UCIe link power management protocols.
- Own the on-chip power management logic: power-state machine, supply sequencing, voltage regulator integration, and the firmware interface for runtime power control.
- Drive power intent (UPF/CPF) authoring and sign-off, coordinating with physical design team on power-domain floorplan, always-on routing, and isolation verification.
- Own the embedded management processor subsystem: processor integration, on-chip SRAM and ROM sizing, boot sequence, fuse and OTP interface, and the firmware execution workplace.
- Define the management register map: the address space through which firmware configures operating modes, reads telemetry, controls power states, and manages DFT operations.
- Specify thermal monitoring integration: on-die temperature sensor placement, readout path to the manageme

📌 Senior Staff (India)
🏢 tylsemi
📍 India