Description:

• Will be responsible for Designing and Implementing DFT techniques
• Should hava a positive understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability.
• Test Modes implementation and verification, scan insertion including on-chip compression.
• Implementing, integrating and verifying memory BIST and boundary scan .
• ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF).
• Basic understanding of complete SOC design and flow.
• Excellent in problem solving and analytical skills
• Excellent communication, team work and networking skills

Primary Skills
• Should Have Valuable understanding of Design and DFT Architecture
• Should have been part of Tapeout SoC
• Well Versed with ATPG Tools & MBIST Tools
•

Secondary Skills
• Team Player, Robust Business Acumen with understanding of organizational issues (conflict resolution between stakeholders)
• Familiarity with Desired Flexibility and adaptability with respect to project management

📌 Dft Engineer Swathy Capgemini Noida (India)
🏢 Coders Brain Technology
📍 India