We are looking for highly skilled VLSI Engineers to join our Offshore Development Center (ODC) supporting next-generation SoC development programs. T
Below are the list of roles we are hiring for:
Senior SoC Verification Engineer – PCIe / DDR / LSIO Verification
Senior DFx Verification Engineer
Senior Formal Verification Engineer
Senior Power-Aware Verification Engineer
Senior Gate-Level Simulation (GLS) Engineer
Key Responsibilities
Develop and execute verification plans for complex SoC and subsystem designs.
Build and maintain SystemVerilog/UVM-based verification environments.
Perform functional, formal, and power-aware verification of SoC designs.
Verify high-speed interfaces such as PCIe, DDR, and Low-Speed IO (LSIO).
Execute Gate-Level Simulations (GLS) with SDF back-annotation.
Analyze simulation failures, debug RTL/design issues, and collaborate with design teams.
Participate in verification planning, coverage closure, regression analysis,
and sign-off activities.
Ensure verification completeness through functional, code, assertion, and toggle coverage.
Work closely with Design, DFT, Physical Design, and Architecture teams throughout the SoC development lifecycle.
Mandatory Skills SoC / Subsystem Verification
Solid hands-on experience in SoC and Subsystem (SS) verification.
Expertise in SystemVerilog and UVM.
Solid debugging and simulation skills.