Please Note:
for achieving Right-first time silicon.

partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities include, but not limited to:
Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
Must have deep functional knowledge of P&R; flows, should be able to catch up quickly on internal flows, adapt.
Implement timing and functional ECO
P&R;, Extraction, Physical verification, work towards STA closure
Build automation flows wherever needed/adapt to existing flows for re-use
Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R;, PV, STA, ECO
Needs to be automation savvy with high expertise in one of the programming languages used in the industry
Clearly know requisites for executing his/her job and lead by example
Bring tangible improvement in TAT with better quality

Minimum Qualifications:
MSEE/MSCS 3+ years (BSEE/BSCS 5+ years)
A deep understanding of backend digital design flow
Proficient in timing constraints, physical constraints




Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
Proficiency in Tcl and Perl
Excellent analytical skills
Shown ability to collaborate in a multi-functional workplace, cross-site or cross-time zone

Broadcom is proud to be an equal chance employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used f

📌 Ic Design Engineer Electronic City
🏢 Broadcom
📍 Electronic City