Job DescriptionExperience: 4 to 12 Years.
NLocation: Bangalore.
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Must have hands-on experience coding in System Verilog/UVM. N
Experience developing testbenches for block level or IP level verification. N
Experience working on subsystem or SoC level would be helpful. N
Candidates should be proactive in communication and be able to work independently to self-manage the deliverable as per the schedules. N
Developing and maintaining block level test benches. N
Vplan, regression and coverage closure. N
Work on testbenches with real number modeling. N
Netlist and Gate level simulations. N
nNotice Period: 30 to 90 days
📌 Sr / Lead Design Verification Bengaluru (India)
🏢 ACL Digital
📍 India
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