Memory Characterization Engineer SRAM

Location: Bengaluru
Work Mode: On-site
Experience: 2 5 Years 1. Role Overview

We are looking for a Memory Characterization Engineer with hands-on experience in SRAM memory characterization, simulation, validation, and Liberty library generation. The role involves transistor-level characterization, SPICE-based simulation and debugging, PEX analysis, timing and power characterization, and .lib generation and validation.

The engineer will work closely with memory design, circuit design, physical design, and library teams to ensure accurate characterization and sign-off quality across relevant PVT conditions.

2. Key Responsibilities

- Perform SRAM memory characterization across process, voltage, and temperature (PVT) corners.
- Develop and execute characterization methodologies for SRAM memory instances and memory compiler outputs.
- Create, modify, and debug SPICE decks, simulation stimuli, testbenches, and test vectors.
- Perform transistor-level simulations using SPICE and FastSPICE simulators.
- Analyze simulation waveforms to identify timing, power, functionality, and convergence issues.
- Perform characterization using PEX-extracted netlists and analyze post-layout parasitic effects.
- Characterize memory timing parameters including setup, hold, access time, recovery, and related timing arcs.
- Perform NLDM and CCS/CCST Liberty characterization for memory libraries.
- Generate and validate Liberty (.lib) files for downstream implementation and STA flows.
- Perform .lib QA, consistency checks, sanity checks, and characterization sign-off validation.
- Debug characterization failures associated with circuit behavior, PVT corners, parasitics, simulator settings,



or characterization setup.
- Work with memory design and CAD/library teams to resolve characterization issues and improve characterization flow quality.

3. Required Qualifications
- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
- 2 5 years of relevant semiconductor industry experience.
- Hands-on experience in SRAM memory characterization and validation.
- Good understanding of SRAM architecture and transistor-level memory circuit behavior.
- Robust understanding of memory timing, power, and characterization methodologies.
- Practical experience with SPICE-based circuit simulation and debugging.
- Experience working with PEX/extracted netlists and post-layout simulations.
- Hands-on exposure to Liberty library generation and validation.

4. Technical Skills Memory Design & Characterization
- SRAM Memory Characterization
- SRAM Design and Validation
- Memory Timing Characterization
- Memory Power Characterization
- PVT Corner Characterization
- Memory Characterization Methodology

SPICE & Simulation
- SPICE / HSPICE-class simulation environments
- FastSPICE Simulation
- SPICE Deck Creation and Modification
- Testbench / Stimulus Development
- Test Vector Creation
- Waveform Analysis and Debugging
- Transistor-Level Circuit Simulation

Post-Layout / PEX
- Parasitic Extraction (PEX)
- Extracted Netlist Simulation
- Post-Layout Characterization
- Deep-Submicron Parasitic Effects
- Process Variation Analysis

Liberty Characterization
- NLDM Characterization
- CCS / CCST Characterization
- Liberty (.lib) Generation
- Liberty Library Validation
- Timing Arc Validation
- Library QA and Sign-Off Checks

📌 Memory Characterization Engineer – SRAM (Bengaluru)
🏢 Best NanoTech
📍 Bengaluru