Meet the Team
Join a dynamic Physical Design team that drives end-to-end SoC implementation, from RTL to tape-out. We work closely with design, verification, and architecture groups to deliver high-performance, low-power solutions. Collaboration, innovation, and technical excellence define our culture—making this an exciting place to grow, lead, and make a real impact.

About the Role
We are seeking a highly skilled Physical Design to join our Silicon Engineering team in Hyderabad. In this role, you will drive the design, implementation, and optimization of advanced SoCs using state-of-the-art physical design methodologies. You will work on challenging synthesis, floorplanning, place-and-route, timing closure, and sign-off flows while mentoring a team of engineers and collaborating with cross-functional groups. This is an excellent chance to contribute to world-class silicon solutions and grow as a technical leader.

Responsibilities

- Lead and execute the end-to-end physical design flow for complex SoCs and IP blocks (RTL handoff to GDSII).

- Define and drive strategies for floorplanning, CTS, placement, routing, and timing closure.

- Own and optimize PPA (Power, Performance, Area) metrics for assigned designs.

- Manage design constraints, synthesis strategies, and sign-off (timing, IR drop, EM, DRC/LVS).

- Collaborate with RTL, DFT, verification, and packaging teams for seamless integration.

- Drive EDA tool automation and methodology improvements for efficiency and scalability.





- Mentor and guide junior engineers to foster technical growth and excellence.

- Work with foundries and vendors on process bring-up, PDK updates, and tape-out readiness.

Requirements

- B.E./B. Tech or M.E./M. Tech in Electrical Engineering, VLSI, or related field.

- 8+ years of experience in ASIC physical design

- Strong hands-on expertise in Synopsys (ICC2, Fusion Compiler, Prime Time), Cadence (Innovus, Tempus), or similar tools.

- Proven background in timing analysis, low-power methodologies, and ECO flows.

- Deep understanding of the architecture-to-GDSII flow and sign-off requirements.

- Excellent problem-solving, leadership, and communication skills.

Preferred Qualification:

- Experience in chip-level integration and hierarchical design methodologies.

- Knowledge of UPF/CPF, power gating, DVFS, and other low-power techniques.

- Familiarity with DFT, STA, and physical verification methodologies.

- Exposure to multi-clock, multi-voltage, and multi-domain designs.

- Previous experience with customer-facing or cross-site collaboration.

Benefits & Perks :

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

- Equity Rewards (RSUs)

- Employee Stock Purchase Plan (ESPP)

- Insurance plans with Outpatient cover

- National Pension Scheme (NPS)

- Adaptable work policy

- Childcare support

📌 Staff Physical Design Engineer (India)
🏢 Silicon Labs
📍 India