Job Summary

This role is responsible for architecting and designing advanced solutions in Design-for-Testability (DFT) and Static Timing Analysis (STA) for complex semiconductor products. The individual leads technical delivery, ensures adoption of best practices, and drives technology initiatives to meet client requirements and industry standards. They provide technical leadership to the team, facilitate upskilling, and ensure project outcomes align with quality and performance benchmarks.

Key Responsibilities
1. Architect DFT and STA solutions using tools such as Synopsys DFT Compiler and PrimeTime, ensuring robust testability and timing closure for ASIC and SoC projects.
2. Lead technical design reviews and mentor team members on implementing scan insertion, ATPG, and timing analysis methodologies using industry-standard EDA tools.
3. Define and enforce DFT and STA processes, integrating technologies like JTAG, boundary scan, and logic BIST to enhance fault coverage and manufacturability.
4. Gather project specifications and translate them into DFT and STA requirements, collaborating with internal design teams to deliver high-quality, client-focused solutions.
5. Drive technology adoption by evaluating emerging DFT/STA tools and methodologies, ensuring solutions remain current and meet evolving client and industry needs.
6.



Develop and deliver training programs on advanced DFT and STA flows, fostering skill development and minimizing delivery risks within the team.
Skill Requirements

1. Expert proficiency in DFT and STA concepts, including scan design, test coverage optimization, and timing analysis.
2. Excellent knowledge of EDA tools such as Synopsys DFT Compiler, Tetramax, PrimeTime, Cadence Encounter, and Mentor Tessent.
3. Expert ability to interpret timing reports, identify violations, and implement fixes for timing closure.
4. Excellent skills in scripting languages (TCL, Perl, Python) to automate DFT and STA flows.
5. Deep understanding of semiconductor design flows, including RTL to GDSII, and integration of DFT/STA at each stage.
6. Excellent communication and leadership skills to guide team members and facilitate technical knowledge transfer.

Other Requirements
1. Optional but valuable: Synopsys Certified DFT/STA Specialist, Cadence Digital Implementation & Signoff Certification.
2. Optional but valuable: IEEE Certified Skilled in VLSI Design.
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📌 Technical Architect - DFT STA (India)
🏢 HCLTech
📍 India