RTL / Verilog Design Engineer (FPGA) :

We are seeking an RTL / Verilog Design Engineer (fresher to 3 years of experience) to develop FPGA-based digital logic for our signal processing, navigation, timing and control products. You will design, simulate, verify and implement RTL for high-pin-count FPGAs used in GNSS receivers, beacon receivers, time servers and antenna control systems.

Key Responsibilities

- Design and develop RTL modules in Verilog/VHDL for FPGA-based products — interface controllers, timing logic, data acquisition and signal processing blocks.
- Develop testbenches and perform functional simulation and verification of RTL designs (ModelSim/Vivado Simulator/Questa).
- Perform synthesis, place-and-route, timing constraint definition (SDC/XDC) and timing closure on Xilinx/Intel FPGA platforms (Vivado/Quartus).
- Implement and integrate interface logic such as UART, SPI, I2C, GPIO, memory controllers (DDR), Ethernet MAC and high-speed serial interfaces.
- Integrate and validate soft processor cores (MicroBlaze/NIOS) and IP cores, and support hardware-software co-design with the firmware team.
- Support FPGA board bring-up and hardware validation using ChipScope/ILA, oscilloscopes and logic analyzers.
- Develop DSP blocks (filters, correlators, NCOs, mixers) for GNSS/beacon signal processing applications under guidance of senior engineers.
- Document design architecture, verification plans, test reports and release notes.

Required Skills:

- Strong fundamentals in digital design — combinational/sequential logic, FSMs, FIFOs,



clock domain crossing and pipelining.
- Good hands-on knowledge of Verilog (or VHDL) coding for synthesis and simulation.
- Familiarity with FPGA design flow: simulation, synthesis, implementation, constraints and timing analysis.
- Exposure to Xilinx Vivado or Intel Quartus toolchains.
- Understanding of common peripheral interfaces (UART, SPI, I2C) and memory basics.
- Ability to write testbenches and debug simulation waveforms.
- Good problem-solving, analytical and documentation skills.
- For experienced candidates (1–3 yrs): project experience in FPGA implementation, timing closure and board-level validation is expected.

Preferred / Added Advantage:

- Academic or project exposure to DSP concepts (FIR/IIR filters, FFT, correlation) or SDR/GNSS signal processing.
- Knowledge of AXI/AVALON bus protocols and SoC FPGA platforms (Zynq).
- Exposure to high-speed interfaces (PCIe, SerDes, Gigabit Ethernet) or DDR memory controllers.
- Familiarity with SystemVerilog or UVM-based verification.
- Scripting skills (TCL, Python) for build and test automation.

What We Offer:

- Opportunity to work on FPGA designs at the heart of mission-critical defense, SATCOM and navigation products.
- Complete design-cycle exposure — RTL to silicon-on-board validation and field qualification.
- Mentorship from an experienced core team in a fast-growing DeepTech company serving leading Indian PSUs and defense organizations.

Advantages:

- Health insurance
- Internet reimbursement
- Provident Fund

Work Location: In person

📌 RTL / Verilog Design Engineer (FPGA) (Sahakar Nagar)
🏢 V3 Novus Private
📍 Sahakar Nagar