Among. The top 4 IT companies, in India ranked by market capitalization and revenue ASIC RTL Lead Bangalopre / Hyderabad / Kochi Mandatory Skill : (RTL Design, RTL Coding & Integration, RTL quality checks (Lint, CDC), IP, targeted for SOC, Static checks, Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI) Senior ASIC Engineer (IP RTL design targeted for SOC, Static checks, some basic protocols) Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Valuable understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols a. PCIe b. DDR c. Ethernet d. I2C, UART,



SPI Expertise in setting up and using tools like a. Spyglass Lint/CDC b. Synopsys DC c. Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc Understanding of processor architecture and/or ARM debug architecture is a plus Able to help and debug issues for multiple subsystems Able to create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews Skills SoC PCIe DDR Ethernet LPDDR Verilog SystemVerilog Xcellium CPU ARM RISC-V Con tact Uday .com Mulya Technologies "Mining the Knowledge Commun ity"

📌 ASIC RTL Design Lead (Kerala)
🏢 Mulya Technologies
📍 Kerala