Company Description
SignOff Semiconductors Pvt. Ltd. is a VLSI design services company headquartered in Bangalore, India, providing end-to-end ASIC and SoC design solutions to global semiconductor companies. Its expertise spans RTL, Verification, DFT, Physical Design, STA, Low Power, Analog/Mixed-Signal, and IP integration across advanced technology nodes.

Role Description
We are looking for a
Physical Design Engineer
with
4–7 years of relevant industry experience
to work on end-to-end
Netlist-to-GDSII
implementation. The role involves floorplanning, placement, CTS, routing, timing closure, ECOs, physical verification, and signoff activities using
Cadence Innovus
. The engineer will work on advanced-node ASIC/SoC designs and collaborate with cross-functional teams to optimize PPA and resolve timing, congestion, and physical verification issues.

Qualifications




- 4–7 years of hands-on
Physical Design
experience, excluding internship/apprenticeship.
- Robust expertise in
Cadence Innovus
and complete PnR flow.
- Experience in
Floorplanning, Placement, CTS, Routing & Timing Closure
.
- Good understanding of
STA, MCMM, Setup/Hold, SDC and timing constraints
.
- Exposure to
DRC/LVS, Tempus, Voltus
and advanced nodes such as 7nm/5nm/3nm is preferred.
- Strong
Tcl scripting
skills; Python/Perl/Shell knowledge is an advantage.
- BE/BTech/ME/MTech in
EEE/ECE/VLSI/Microelectronics
or related fields.
- Notice Period:
Maximum 30–45 days;
15 days/Immediate preferred
.

📌 Physical Design Engineer (Bengaluru South)
🏢 SignOff Semiconductors
📍 Bengaluru South