Silicon Engineering / 3-10 Years

Design for Test (DFT)

Role: Design for Test (DFT) Experience: 3 10 Years
Locations: Bangalore / Hyderabad / Ahmedabad

Job Description:

We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether you are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles that will challenge and grow your skills in advanced silicon testing. You will be responsible for the end-to-end DFT ow, from RTL to nal pattern delivery, across complex IP, subsystem, and SOC designs.

Core Responsibilities:
- End-to-end ownership of the DFT implementation ow from RTL to nal pattern sign-off.
- Scan architecture denition and implementation at RTL and gate level, including EDT and OCC.
- Execution of block-level ATPG, DRC analysis, and coverage optimization.
- Handling of pattern simulations, including both timing and non-timing simulations.
- SOC-level integration, including pattern retargeting to subsystem and full-chip levels.
- Integration, simulation, and debug of MBIST, IJTAG,



and Boundary Scan (JTAG).
- Independent debugging of DFT simulations and netlist-related issues.
- Close collaboration with design, verication, and physical design teams to ensure DFT readiness.
- Ownership of DFT sign-off activities and deliverables.

Key Responsibilities:
- Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.
- Perform scan insertion, ATPG generation, and pattern validation at block and top levels.
- Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.
- Dene and execute DFT strategies aligned with project requirements and schedules.
- Support pre-silicon and post-silicon test requirements.
- Serve as the DFT point of contact for assigned projects, responsible for verication and test readiness sign-off.

Technical Requirements:

Must-Have Skills:
- Robust experience in netlist handling and ATPG simulations.
- Proven expertise in b

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