Senior RTL Design Engineer

Location: Hyderabad

Experience: 3–6 Years

Role Overview

We are looking for a Senior RTL Design Engineer with solid hands-on expertise in Ethernet-based SoC/IP design, RTL development, and design quality checks.

Key Responsibilities

- Develop and integrate synthesizable RTL for complex SoC/IP designs.
- Strong hands-on experience with Ethernet protocols/IP and high-speed networking designs.
- Translate microarchitecture specifications into efficient RTL.
- Perform Lint, CDC/RDC and RTL quality checks using SpyGlass.
- Debug and resolve RTL, CDC, lint and functional issues.
- Collaborate with Architecture, DV, STA and Physical Design teams.
- Drive RTL optimization for PPA, timing, area and power.

Core Technical Skills

- Strong Verilog/SystemVerilog RTL design experience.




- Solid microarchitecture understanding and ability to work from specifications.
- Strong Ethernet knowledge — MAC/PCS/PHY, 10G/25G/100G/400G exposure preferred.
- Hands-on experience with SpyGlass Lint & CDC.
- Strong understanding of CDC, reset architecture, clocking and RTL coding practices.
- Experience with synthesis, timing and PPA optimization.
- Strong debugging and problem-solving skills.

Ideal Candidate: A hands-on RTL engineer with strong Ethernet + Microarchitecture + Lint/CDC + SpyGlass expertise and experience delivering production-quality SoC/IP designs.

📌 Senior RTL Design Engineer (Hyderabad)
🏢 Leadsoc Technologies
📍 Hyderabad