Position: Senior Engineer HDD

Experience: 5–7 Years

Location: Chennai

We are looking for an experienced FPGA/RTL Design Engineer with strong expertise in high-speed digital hardware design for defense and aerospace applications. The ideal candidate should have hands-on experience in FPGA development, RTL design, timing closure, and high-speed interface protocols.

Key Responsibilities

- Generate hardware requirements and perform RTL design using Verilog/VHDL.
- Develop FPGA-based digital designs following the DO-254 development lifecycle.
- Perform synthesis, static timing analysis (STA), timing closure, and design constraint optimization.
- Work on Xilinx/Vivado or Intel (Altera)/Quartus FPGA platforms.
- Design and implement high-speed interfaces such as PCIe, DDR, JESD, Ethernet, and ARINC protocols.
- Develop, maintain, and enhance simulation and verification environments.
- Optimize FPGA designs for Area, Power, and Performance.
- Perform system-level debugging using Tcl scripting, logic analyzers, and debugging tools.




- Collaborate with cross-functional teams throughout the design, verification, and validation phases.

Required Skills

- Solid proficiency in Verilog and/or VHDL.
- Hands-on experience with Vivado or Quartus.
- Expertise in Static Timing Analysis (STA), floorplanning, and timing closure.
- Experience with FPGA architectures (Xilinx/Altera).
- Strong understanding of PCIe, Ethernet, Multi-Gigabit Transceivers (SERDES).
- Experience with high-speed interfaces including PCIe, DDR, JESD, and Ethernet.
- Good knowledge of Digital Design, Signal Processing, and analytical problem-solving.
- Experience balancing architectural trade-offs between Area, Power, and Speed.
- Familiarity with Tcl scripting and hardware debugging tools.
- Experience in RADAR Digital Signal Processing is highly preferred.
- Knowledge of DO-254 standards is mandatory.

📌 Senior Engineer (Chennai)
🏢 Vysystems
📍 Chennai