Company Description:

ASIP Technologies is a complete turnkey solutions provider specializing in package design, bumping, assembly, testing, and dropship services for semiconductor technologies. The company focuses on delivering best-in-class quality and service, supporting customers across the full product lifecycle.

ASIP Technologies partners closely with clients to provide reliable, scalable manufacturing and test solutions. Team members work in a quick-paced, technology-driven environment with opportunities to contribute to high-impact projects and continuous innovation. More on: www.asip-tech.com.

Role Description : Senior DFT Engineer is responsible for implementing and validating DFT structures, including TAP, JTAG, Boundary Scan, Memory BIST, Scan Logic, Scan Insertion, etc. and tasks including Scan Insertion, ATPG, Simulations for an assigned block, IP or SoC, ensuring all the Test KPIs like test coverage, timing and area targets are met. The role includes cross-functional collaboration with Design, Frontend, Backend, Timing closure teams to resolve all DFT-related issues and contribute to the continuous improvement of the quality of the Test patterns. The role also involves mentoring and training the junior DFT engineers within the team.

Responsibilities :

- Implement DFT structures for an assigned block, IP or SoC, including TAP, JTAG, Boundary Scan, MBIST, Scan, etc.
- Demonstrate deep expertise in Tessent (Scan/MBIST/IJTAG/SSN/BScan, ATPG) Formal Verification, Timing Analysis and Physical DRCs cleanup
- Scan ATPG – Low Coverage Debug, Pattern Optimization and other Test time reduction tasks • Debug and Diagnosis of Post-Silicon ATE Fail data
- Yield Analysis, DPM calculation of High Volume Manufacturing




- Handling third-party IPs, including tracing scan chains, reviewing vendor documentation and developing custom ATE patterns
- Debug DFT-related failures, coverage gaps, DRC violations, Scan/ATPG issues and drive fixes to closure
- Collaborate with Frontend (FE) and Backend (BE) teams to proactively identify and resolve DFT-related issues including RTL testability concerns, DFT timing constraints & DRC cleanup
- Contribute to documentation of DFT implementation, validation, coverage results and known limitations for the assigned scope
- Suggest improvements to existing DFT flows, scripts and automation

- Qualifications :
- Bachelor’s/ Master’s degree / Ph.D in Electrical Engineering, Electronics, or a related field, with relevant industry experience in DFT or test engineering.
- Effective communication and collaboration skills, with the ability to work in cross-functional teams and mentor junior engineers.
- Attention to detail, strong analytical skills, and a commitment to quality and continuous improvement.

Skills & Expertise:

Essential

- 4+ years of hands-on experience in DFT
- Hands-on experience in TAP, JTAG, Boundary Scan, MBIST and Scan/ATPG
- Hands-on experience on Tessent tools
- Exposure to EDT, OCC, SSN, MBIST repair, debug
- Exposure to any Formal Verification tools
- Solid understanding of Digital Design fundamentals, Timing Analysis, Physical Design

Preferred

- Scripting and Automation exxperience
- Experience on a full project cycle from design to Tapeout and ATE Bringup
- Familiarity with Low-power design concepts
- Prior experience mentoring Junior engineers on DFT concepts and tools
- Strong Communication and Presentation skills
- Ability to work in a Global Work environment

📌 Senior DFT Engineer (Hyderabad)
🏢 ASIP Technologies
📍 Hyderabad