Job Description

We are seeking an experienced and highly technical Backend Physical Design Engineer to drive the physical implementation of our next-generation, high-performance SoCs. You will own the complete RTL-to-GDSII flow, focusing heavily on power recovery, clock tree optimization, and pushing aggressive PPA metrics on advanced technology nodes

Key Responsibilities
RTL-to-GDSII Execution: Own and drive the end-to-end physical design implementation, including floor planning, synthesis, placement, Clock Tree Synthesis (CTS), and routing.
PPA Optimization: Fine-tune the design to meet stringent Power, Performance, and Area (PPA) targets. Employ advanced techniques like multi-voltage domains, power gating (UPF), and datapath optimization to minimize power while maximizing speed.
Timing Closure & STA: Drive Static Timing Analysis (STA)



across multiple corners and operating modes. Resolve setup/hold violations, signal integrity issues, and clock domain crossing constraints.
Physical & Formal Verification: Execute Design Rule Checks (DRC), Layout Versus Schematic (LVS), electromigration/IR drop (EMIR) analysis, and Equivalence Checking (LEC/Formality) to ensure design reliability and manufacturability.
Cross-Functional Collaboration: Work closely with RTL (Frontend), DFT, and Signoff teams to iterate on designs and structural changes for optimal PPA.
Programming/Scripting: Solid scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies

📌 Principal /sr Staff Pd Implementation Expert Bengaluru
🏢 renesas electronics
📍 Bengaluru