Hi We are hiring a hands-on ASIC RTL engineer with strong RTL coding skills who owns micro-architecture and RTL development from spec to silicon. This role is about writing real RTL that goes into production chips. What youll do Define and own micro-architecture Write, review, and own high-quality synthesizable RTL code in SystemVerilog / Verilog Build and integrate SoC or large subsystem blocks Drive timing, power, and area closure with physical design teams Lead design reviews, debug issues, and support silicon bring-up and post-silicon validation Work closely with DV on test plans, assertions, and coverage FPGA/emulation may be used only as a secondary validation aid What were looking for 8+ years of hands-on ASIC RTL coding experience (FPGA experience does not count toward this requirement)



Multiple production ASIC tapeouts with clear ownership Robust RTL coding and micro-architecture ownership (non-negotiable) Solid understanding of clock/reset design and low-power techniques (UPF, retention, isolation) Experience with AMBA protocols: AXI, ACE, AHB, APB Proven collaboration with synthesis, PnR, DFT, ECO, and timing-closure teams Direct silicon bring-up experience for owned blocks Good to have Exposure to coherency, cache/memory subsystems, DDR, PCIe, security or crypto blocks SVA for design-level assertions Tcl/Python scripting to improve RTL productivity What wont be considered FPGA-only or FPGA-heavy roles Lint/CDC-only, integration-only, or tool-running profiles Pure management or architect-only roles without recent hands-on RTL work Cheers, Shahid

📌 RTL Design Engineer – ASIC / SoC (India)
🏢 Proxelera
📍 India