? We’re Hiring – Memory Layout Engineer | Bangalore ?

We are looking for experienced Memory Layout Engineers in Bangalore.

? Location: Bangalore

? Experience: 4–10 Years

? Qualification: B.E./B.Tech/M.E./M.Tech in Electrical/Electronics Engineering

? Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm & GF Nodes

? Key Skills:

- Memory Layout – SRAM/DRAM, Memory Compiler IPs
- Bitcell Array, Control Logic, Sense Amplifiers, I/O, Decoders & Memory Periphery
- Top-Level Memory Integration
- DRC, LVS, DFM, Density Verification & Physical Closure
- IR/EM and Reliability Challenges
- Cadence / Synopsys Layout Tools
- Mentor / Cadence / Synopsys Physical Verification Tools
- FinFET Design Rules & Ultra-Deep Sub-Micron Layout




- Memory Architecture & Bitcell Layout Concepts
- Area, Power, Speed, Yield & Manufacturability Optimization

? ? Ideal Candidates:

Candidates with solid hands-on experience in advanced-node memory layout, memory compiler development, SRAM/DRAM layouts and physical verification are encouraged to apply.

? Interested candidates can DM me or share their updated resume.

#Hiring #MemoryLayout #VLSI #ASIC #Semiconductor #PhysicalDesign #CustomLayout #SRAM #DRAM #MemoryCompiler #FinFET #Cadence #Synopsys #BangaloreJobs #VLSIJobs #SemiconductorJobs

📌 Memory Layout Engineer | 4–10 Years | Bangalore | Immediate to 15 day Notice only (Bengaluru)
🏢 Headway Tek
📍 Bengaluru