Company Description LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise, supporting the complete chip development lifecycle from circuits to RTL, layout, physical design, verification, and characterization. Founded in 2018, the company has grown into a trusted partner for global semiconductor organizations, offering scalable offshore development centers and engineering teams across India and Canada. LeadIC delivers high-quality design services across key domains such as custom and analog layout, mixed-signal circuit design, digital design and RTL development, design verification, physical design, STA, DFT, IP characterization, and FPGA-based prototyping.

The company emphasizes an engineering culture built on ownership, quality-driven execution, and flexible engagement models tailored to product-driven teams. Long-term relationships with leading semiconductor companies reflect LeadIC’s reliability, technical depth, and focus on accelerating silicon success.

Role Description This is a full-time Design Verification Engineer role based in Bengaluru with a hybrid work arrangement that allows partial work from home.

The Design Verification

Engineer will be responsible for developing and executing verification plans, writing and reviewing testbenches, and creating test cases to ensure functional correctness of complex RTL designs. Day-to-day activities include building verification environments, performing functional and formal verification, debugging failures, analyzing coverage, and collaborating closely with RTL designers, architects, and validation teams.



The role also involves contributing to verification methodology improvements, maintaining documentation, and supporting sign-off criteria for IP and full-chip verification.

The engineer is expected to work proactively within cross-functional teams to meet project schedules and quality targets.

Qualifications

- Robust functional verification skills, including experience with testbench development, test planning, coverage analysis, and debugging.
- Knowledge of formal verification methodologies and tools, with the ability to apply formal techniques to critical blocks and corner cases.
- Proficiency in RTL design, including understanding of HDL languages (such as Verilog/SystemVerilog) and familiarity with synthesis and implementation flows.
- Solid grasp of computer architecture concepts, such as pipelines, caches, memory subsystems, and interconnects, to interpret specifications and verification requirements.
- Demonstrated debugging skills across simulation and lab environments, including root-cause analysis of functional and performance issues.
- Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or a related discipline.
- Experience with industry-standard EDA tools for simulation and formal verification; exposure to UVM or similar verification methodologies is an advantage.
- Strong analytical and communication skills, ability to collaborate in cross-site teams, and a high level of ownership toward project deliverables.
- Prior experience in VLSI design and verification for ASIC or FPGA projects is

📌 Design Verification Engineer ( 4+ yrs) (Bengaluru)
🏢 leadIC Design
📍 Bengaluru