Position:
Associate Engineer-DFT
Job Description:
Technical:
3+ years of hands-on experience in defining DFT architecture and setting-up DFT flow, Scan insertion, MBIST insertion and Boundary Scan implementation at Fullchip level
ATPG and Pattern verification at Fullchip level
Implement and debug iJTAG and IEEE **** core wrapper-based architecture
Create DFT modes timing constraints
Pattern diagnosis and debug the ATE pattern failures
Very valuable debugging skills
Scripting for flow automation
Should have worked on below Tools:
Synopsys tools: DFTMAX, TetraMAX, VCS, Verdi and PT
OR Cadence tools: Genus and Modus, NC-SIM/Irun, Sim-Vision, LEC
OR Mentor Graphics tools: Tessent tool chain, TestKompress, Questa
Familiarity with ATE and LBIST will be plus
Location:
IN-GJ-Ahmedabad, India-Aryan Bld-2 (eInfochips)
Time Type:
Full time
Job Category:
Engineering Services