Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelor's or Master's in Electrical Engineering or related field 8 years of experience in SOC logic synthesis and timing constraints Must hold a Bachelor's and/or a Master's in Electrical Engineering with at least 8+ years' experience in SOC logic synthesis and timing constraints Experience required in one or more tools/areas: Synthesis (DCG/FC/Genus), Formal Verification (LEC/Formality), STA (Primetime) Strong expertise in STA timing analysis basics,



AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling. Hands-on experience with STA tools - Prime-time, Tempus Have experience working on timing convergence at Chip-level and Hard-Macro level. Valuable understanding of timing constraints development Good understanding low power and power simulations using ptpx/power artist/conformal low power Could be substituted for experience in Physical Design or Circuit Design, with eagerness to learn front-end implementation tool flows Should have good analytical ability, problem solving skills and be a self-starter Candidate should be able to lead and work in a team environment Good scripting skills using tcl/perl languages

📌 WLAN Implementation Engineer, Staff (Chennai)
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