- Design and develop embedded memory IPs (SRAM, Register Files, ROM).
- Perform transistor-level circuit design, simulation, and optimization.
- Optimize memory for timing, power, and area (PPA).
- Collaborate with Layout, Verification, and Physical Design teams.
- Support silicon debug and mentor junior engineers (Lead role).
Preferred candidate profile
- 515 years of experience in Memory Design with expertise in SRAM and custom circuit design.
- Hands-on experience with Cadence Virtuoso, Spectre, HSPICE, or equivalent EDA tools.
- Solid understanding of CMOS circuit design, PVT analysis, timing, power, and area optimization.
- Experience in AI, HPC, or Data Center SoC projects is preferred.
- Strong problem-solving, collaboration, and mentoring skills for senior/lead roles.