Sr. Staff Engineer, EMIR/Power Integrity (Bengaluru)

Sr. Staff Engineer, EMIR/Power Integrity (Bengaluru)

21 Aug
|
Ayar Labs
|
Bengaluru

21 Aug

Ayar Labs

Bengaluru

Sr. Staff Engineer, EMIR / Power Integrity

Location: Bengaluru (on-site, flexible schedule)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we use light instead of electricity to move data faster, farther, and with a fraction of the energy required to fuel the explosive growth of AI models.

Backed by industry leaders including NVIDIA, AMD, and Intel, and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to enabling next-generation AI scale-up architectures.

The Sr. Staff Engineer, EMIR / Power Integrity will own full-chip power-integrity analysis, closure, and signoff for advanced-node SoCs integrating high-speed digital, analog/mixed-signal, and photonics-interface components.

This is a hands-on technical-lead role spanning early architecture and floorplanning through final tapeout. The successful candidate will not simply run EMIR tools; they will interpret results, identify risks, define corrective actions,



and drive cross-functional closure across physical design, circuit design, package, and signoff teams.

Key Responsibilities
* Own full-chip static and dynamic IR-drop, electromigration, and power-integrity analysis from early floorplanning through final tapeout.
* Define EMIR signoff methodology, scenario coverage, guardbands, acceptance criteria, waiver processes, and tapeout-quality gates.
* Develop and optimize full-chip power-delivery strategies, including power-domain planning, power-grid architecture, bump assignment, macro power connections, via structures, and decap allocation.
* Perform vectorless and vector-based dynamic voltage-drop analysis using realistic VCD, FSDB, SAIF, and workload-derived activity.
* Analyze functional, calibration, power-up, scan-shift, scan-capture, BIST, and other high-current operating modes.
* Incorporate package, interposer, bump, and RDL parasitic models into chip-level

📌 Sr. Staff Engineer, EMIR/Power Integrity (Bengaluru)
🏢 Ayar Labs
📍 Bengaluru

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