Senior / Staff Engineer, ASIC Design Verification (Hyderabad)

Senior / Staff Engineer, ASIC Design Verification (Hyderabad)

21 Aug
|
Important Group
|
Hyderabad

21 Aug

Important Group

Hyderabad

An expert level experience with either NAND, DDR and PCIe IP/sub-systems. Highly experienced with defining block, sub-system and SOC top level test plans. An expert level with developing UVM-based SV test-benches. Deep understanding and knowledge of verification methodologies flows and quality metrics. At least 3+ years of relevant experience in NAND, DDR and PCIe verification. Solid and relevant expertise with ASIC simulation tools and advanced verification methods. Expert level in verification languages such as UVM and System Verilog. Relevant experience with writing block-level and SoC test-plans. in electrical engineering, computer science with extensive industry experience.

📌 Senior / Staff Engineer, ASIC Design Verification (Hyderabad)
🏢 Important Group
📍 Hyderabad

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