STA & Synthesis Lead Engineer

Experience:
5+ Years

Education:
B.Tech/B.E./M.Tech/M.E. in VLSI, Electronics, Electrical Eng

Location:
Bangalore

We are looking for an experienced
STA & Synthesis Lead Engineer
with hands-on experience in Logic synthesis, static timing analysis, timing closure, and design optimization. The ideal candidate will have solid expertise in
PPA optimization, MMMC timing analysis, SDC constraints, ECO implementation, and formal equivalence checking
, with the ability to work closely with RTL, DFT, and Physical Design teams.

The candidate will be responsible for driving synthesis and timing sign-off activities from RTL through implementation, identifying timing bottlenecks, and delivering optimized designs that meet
Power, Performance, and Area (PPA)
targets.

Key Responsibilities
Logic Synthesis & PPA Optimization
Perform
physical-aware RTL-to-gate synthesis
for complex digital designs.
Optimize synthesis results for
Power, Performance, and Area (PPA)
targets.
Analyze synthesis reports and identify prospects for timing, area,



and power improvements.
Work with RTL designers to resolve synthesis-related issues and improve RTL quality.
Support synthesis flows across block-level and top-level designs.
Constraint Development & Management
Develop, review, validate, and debug
SDC timing constraints
for block-level and top-level designs.
Define and maintain constraints for
functional, scan, and DFT modes
.
Handle clock definitions, generated clocks, clock relationships, I/O constraints, false paths, multicycle paths, and case analysis.
Debug constraint-related timing issues and ensure constraint completeness and correctness.
Static Timing Analysis & Sign-Off
Perform
Static Timing Analysis (STA)
across
Multi-Corner Multi-Mode (MMMC)
scenarios.
Drive timing sign-off for
setup, hold, recovery, removal, and clock-gating checks
.
Analyze critical paths, timing violations, clock interactions, and design bottlenec

📌 Sta And Synthesis Engineer Bangalore Urban (India)
🏢 Mirafra Technologies
📍 India