We are seeking a skilled and detail-oriented Physical Design Engineer with 3+ years of experience to join our semiconductor implementation team. In this role, you will be responsible for the block-level and chip-level physical design of complex, high-performance integrated circuits. You will own the implementation process from synthesis/netlist handover through to GDSII tape-out, ensuring strict timing, power, and area (PPA) goals are met.
Location: Bengaluru and Pan India.
Role & responsibilities
Netlist-to-GDSII Ownership: Drive the complete physical design flow for complex blocks and subsystems.
Floor planning & Power Design: Develop productive block floorplans, manage macro placement, and design robust Power Distribution Networks (PDN).
Placement & Routing: Execute timing-driven placement, Clock Tree Synthesis (CTS), and signal routing using industry-standard EDA tools.
Timing & Signal Integrity Closure: Perform static timing analysis (STA) to identify and fix setup, hold, and crosstalk violations across various PVT corners.
Engineering Change Orders (ECO):
Implement pre-layout and post-layout functional and timing ECOs to meet project deadlines.
Physical Verification: Run and debug Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Antenna checks to ensure a clean tape-out.
Power & Integrity Analysis: Perform static and agile IR drop analysis, electromigration (EM) checks, and implement fixes.
Flow Automation: Write and maintain Tcl, Perl, or Python scripts to automate design steps and improve turnaround time.
Preferred candidate profile
Experience: Minimum 3+ years of hands-on industry experience in ASIC/SoC physical design.
Education: Bachelors or Masters degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
EDA Tools: Robust proficiency in Cadence Innovus or Synopsys ICC2/Fusion Compiler, along with Calibre for physical verification.
Technology Nodes: Proven experience working on adva