We are seeking a skilled and detail-oriented Design Verification Engineer with 3+ years of experience to join our semiconductor verification team. In this role, you will be responsible for developing and executing verification plans for complex, high-performance IP blocks and SoC subsystems. You will own the verification process from testbench development through to functional closure, ensuring complete coverage and robust, bug-free silicon.
Role & responsibilities
Testbench Development: Develop and maintain UVM-based, reusable verification settings for IP and SoC-level verification.
Verification Planning: Create comprehensive verification test plans covering functional, corner-case, and negative scenarios.
Simulation & Debug: Execute simulations, debug failures using waveform viewers, and root-cause issues down to RTL.
Coverage Closure: Develop functional and code coverage models; analyze and close coverage gaps.
Assertion-Based Verification: Write System Verilog Assertions (SVA) to verify protocol and design behavior.
Regression Management:
Set up and maintain regression suites; triage and debug nightly regression failures.
Formal Verification: Apply formal methods/tools for targeted block-level property checking where applicable.
Cross-functional Collaboration: Work closely with RTL design, DFT, and architecture teams to align verification with design intent.
Required Qualifications
Experience: Minimum 3+ years of hands-on industry experience in ASIC/SoC design verification.
Education: Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
Verification Languages/Methodology: Robust proficiency in System Verilog and UVM.
Tools: Experience with industry-standard simulators (Synopsys VCS, Cadence Xcelium) and debug tools (Verdi/SimVision).
Technical Skills: Deep understanding of functional coverage, assertion-based verification, and constrained-random testing.
Soft Skills: Exc