Job Area
Engineering Group, Engineering Group > Hardware Engineering
General Summary
Job Description
This role offers a position in system power management IP cores and subsystem design, targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets.
Key Responsibilities
- Micro-architecture and RTL design for IP Cores / subsystems.
- Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence.
- Enable SW teams to use HW blocks.
- Qualify designs using static tool checks including Lint, CDC, CLP etc.
- Synthesis, LEC and Netlist CLP
- Report status and communicate progress against expectations.
Preferred Qualifications
- 3 to 8 years of solid experience in RTL design for ASICs
- Expertise in RTL coding in Verilog/SV of complex designs with multiple clock domains and multiple power domains
- Familiar with UPF and power domain crossing
- Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP
- Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
- Experience in low power design methodology and clock domain crossing designs
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in formal verification with Cadence LEC
- Understanding of full RTL to GDS flow to interact with DFT and PD teams
- Expertise in Perl/TCL/Python language
- Experienced in database management flows with Clearcase/Clearquest.
- Expertise in post-Si debug is a plus
- Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members.
- Team player, self-motivated, should be able to work with minimal supervision.
Minimum Qualifications
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Elect