About SiTime

SiTime is the Precision Timing company.
Job Summary

The Sr. Layout Design Engineerwill lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to developing standard layout methodologies across sites. Contribute to build process and procedures to achieve high layout quality
Responsibilities:
Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones
Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
Perform schematic-driven layout and design constraints
Design die-area effective layouts according to circuit designer requirements
Perform block or top-level layout designs
Perform floor-planning, power line planning, shielding,



and device-matching layout
Verify layouts. Pass DRC, LVS, and ERC
Contribute to various chip-level routing and layout needs
Perform chip level integration, verifications, and tape-out
Support other projects as needed by management
Train junior layout engineers and offshore layout contractors
Contribute to developing common best practices and workflow across all sites
Contribute to build process and procedures to achieve high layout quality
Qualifications & Requirements:
BA/BS Degree in Layout Design or related field or equivalent experience
10 years’ experience with layout design for analog and full-custom digital blocks
Experience TSMC 180nm, 65nm, 22nm process technologies
Proficient in using layout editing tools in the Cadence Virtuoso design setting
Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
Conceptual understanding of layout topics suc

📌 Sr Layout Design Engineer Bengaluru
🏢 SiTime
📍 Bengaluru