Job Requirements
Hands on Technical lead with SoC & Netlist level DFT execution experience and one can guide juniors
Scan Insertion: Stitching every flop in the design into shift registers (scan chains) to set the chip to any state and observe any state.
ATPG (Automatic Test Pattern Generation): Running tools to generate patterns that detect manufacturing defects via the scan chains.
MBIST (Memory BIST): Inserting on-chip memory test logic to allow RAMs and ROMs to self-test in the field.
Boundary Scan and JTAG: Utilizing boundary scan and JTAG techniques for testing.
Collaboration: Working closely with design and verification teams to optimize for test efficiency and fault isolation.
Integration: Integrating test structures within the design of electronic components to facilitate effective testing throughout the product lifecycle
📌 Dft Lead Bengaluru
🏢 Quest Global
📍 Bengaluru
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